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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Initialization
Initialization
Low-power SDRAM devices must be powered up and initialized in a predefined man-
ner. Using initialization procedures other than those specified may result in undefined
operation. After power is simultaneously applied to V DD and V DDQ and the clock is sta-
ble (a stable clock is defined as a signal cycling within timing constraints specified for
the clock ball), the device requires a 100 μ s delay prior to issuing any command other
than a COMMAND INHIBIT or NOP. Starting at some point during this 100 μ s period
and continuing at least through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
After the 100 μ s delay is satisfied by issuing at least one COMMAND INHIBIT or NOP
command, a PRECHARGE command must be issued. All banks must then be pre-
charged, which places the device in the all banks idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the device is ready for mode register programming. Be-
cause the mode register powers up in an unknown state, it should be loaded prior to
issuing any operational command.
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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